In recent years, a successive comparison A/D (Analog-to-Digital) converter is implemented in a relatively simple circuitry, is highly compatible with the CMOS process, and achieves a relatively short conversion time, thus being widely used for various purposes. The successive comparison A/D converter generally includes a DAC (Digital-to-Analog Converter), a comparator, and a DAC control circuit.
As the operation of the overall successive comparison A/D converter, first, in the sampling period, input voltages are sampled and held as sample voltages. In the next comparison period, the voltages to be compared are successively compared with the sample voltages.
In other words, in one comparison operation by the comparator, one voltage to be compared corresponding to one digital code is compared with the sample voltage to determine the value of the voltage to be compared relative to the sample voltage.
The DAC control circuit changes the digital code in accordance with the comparison result output from the comparator to, in turn, change the voltage value to be compared from a large-step voltage to a small-step voltage, and N comparison operations are successively executed to obtain N-bit digital data by conversion.
When, for example, the edge count becomes different from an expected value (a count equal to the resolution) due to PVT (Process/Voltage/Temperature) fluctuations, the successive comparison A/D converter, as described above, changes the delay amount adjustment code in steps of one code to adjust the amount of delay and, in turn, adjust the loop operating frequency.
In other words, in the comparison period, N comparison operations are successively executed by the comparator, based on the edges of a predetermined pulse signal (asynchronous clock: φc), to convert an input signal into N-bit digital data.
Therefore, when the edge count value is smaller than the resolution, a predetermined number of A/D conversions can hardly be performed, thus lowering the A/D conversion accuracy. On the other hand, when the edge count value is larger than the resolution, the operating speed may be so high as to degrade the A/D conversion accuracy.
As described above, when PVT fluctuations occur (e.g., the voltage, the temperature, or other factors rapidly change), it takes a long time for the successive comparison A/D converter to adjust the amount of delay. This means that it takes much time for the edge count value (the number of determination operations) and the resolution to become equal to each other.
It may be possible to change the voltage or the temperature to allow setting of an appropriate amount of delay corresponding to each condition in advance. In this case, the adjustment period can be shortened but the examination cost, the circuit area, and the power consumption rise.
By the way, in the past, various driving clock adjusting techniques of the successive comparison A/D converter have been proposed.
Patent Document 1: Japanese Laid-open Patent Publication No. 2011-061597
Patent Document 2: Japanese Laid-open Patent Publication No. 2012-039475
Patent Document 3: Japanese Laid-open Patent Publication No. 2012-182638
Patent Document 4: Japanese Laid-open Patent Publication No. H07 (1995)-170185